Formal design of an asynchronous DSP counterflow pipeline: A case study in Handshake Algebra

M. B. Josephs; P. G. Lucassen; J. T. Udding; T. Verhoeff

Formal design of an asynchronous DSP counterflow pipeline: A case study in Handshake Algebra

M. B. Josephs^*, P. G. Lucassen, J. T. Udding, T. Verhoeff

^*Corresponding author for this work

London South Bank University

Research output: Contribution to conference › Paper › peer-review

8 Citations (Scopus)

Original language	English
Pages	206-215
Number of pages	10
Publication status	Published (VoR) - 1994
Event	Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems - Salt Lake City, UT, USA Duration: 3 Nov 1994 → 5 Nov 1994

Conference

Conference	Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems
City	Salt Lake City, UT, USA
Period	3/11/94 → 5/11/94

Cite this

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title = "Formal design of an asynchronous DSP counterflow pipeline: A case study in Handshake Algebra",

author = "Josephs, \{M. B.\} and Lucassen, \{P. G.\} and Udding, \{J. T.\} and T. Verhoeff",

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language = "English",

pages = "206--215",

note = "Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems ; Conference date: 03-11-1994 Through 05-11-1994",

}

Formal design of an asynchronous DSP counterflow pipeline: A case study in Handshake Algebra. / Josephs, M. B.; Lucassen, P. G.; Udding, J. T. et al.
1994. 206-215 Paper presented at Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, Salt Lake City, UT, USA.

Research output: Contribution to conference › Paper › peer-review

TY - CONF

T1 - Formal design of an asynchronous DSP counterflow pipeline

T2 - Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems

AU - Josephs, M. B.

AU - Lucassen, P. G.

AU - Udding, J. T.

AU - Verhoeff, T.

PY - 1994

Y1 - 1994

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M3 - Paper

AN - SCOPUS:0028751982

SP - 206

EP - 215

Y2 - 3 November 1994 through 5 November 1994

ER -

Formal design of an asynchronous DSP counterflow pipeline: A case study in Handshake Algebra

Conference

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