Gate-level modelling and verification of asynchronous circuits using CSPM and FDR

Mark B. Josephs

doi:10.1109/async.2007.19

Gate-level modelling and verification of asynchronous circuits using CSP_M and FDR

Mark B. Josephs^*

^*Corresponding author for this work

London South Bank University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Citations (Scopus)

Original language	English
Title of host publication	13th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2007
Publisher	IEEE Computer Society
Pages	83-94
Number of pages	12
ISBN (Print)	9780769527710
DOIs	https://doi.org/10.1109/async.2007.19
Publication status	Published (VoR) - 2007
Event	13th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2007 - Berkeley, CA, United States Duration: 12 Mar 2007 → 14 Mar 2007

Publication series

Name	Proceedings - International Symposium on Asynchronous Circuits and Systems
ISSN (Print)	2643-1394
ISSN (Electronic)	2643-1483

Conference

Conference	13th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2007
Country/Territory	United States
City	Berkeley, CA
Period	12/03/07 → 14/03/07

Access to Document

10.1109/async.2007.19

Cite this

@inproceedings{8ae7fa74cebe42188f26bcd4bcff460d,

title = "Gate-level modelling and verification of asynchronous circuits using CSPM and FDR",

author = "Josephs, {Mark B.}",

year = "2007",

doi = "10.1109/async.2007.19",

language = "English",

isbn = "9780769527710",

series = "Proceedings - International Symposium on Asynchronous Circuits and Systems",

publisher = "IEEE Computer Society",

pages = "83--94",

booktitle = "13th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2007",

note = "13th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2007 ; Conference date: 12-03-2007 Through 14-03-2007",

}

Josephs, MB 2007, Gate-level modelling and verification of asynchronous circuits using CSP_M and FDR. in 13th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2007., 4137035, Proceedings - International Symposium on Asynchronous Circuits and Systems, IEEE Computer Society, pp. 83-94, 13th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2007, Berkeley, CA, United States, 12/03/07. https://doi.org/10.1109/async.2007.19

Gate-level modelling and verification of asynchronous circuits using CSP_M and FDR. / Josephs, Mark B.
13th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2007. IEEE Computer Society, 2007. p. 83-94 4137035 (Proceedings - International Symposium on Asynchronous Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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U2 - 10.1109/async.2007.19

DO - 10.1109/async.2007.19

M3 - Conference contribution

AN - SCOPUS:84886915460

SN - 9780769527710

T3 - Proceedings - International Symposium on Asynchronous Circuits and Systems

SP - 83

EP - 94

BT - 13th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2007

PB - IEEE Computer Society

T2 - 13th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2007

Y2 - 12 March 2007 through 14 March 2007

ER -

Gate-level modelling and verification of asynchronous circuits using CSP_M and FDR

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