Modelling and verification of delay-insensitive circuits using CCS and the Concurrency Workbench

Hemangee K. Kapoor*, Mark B. Josephs

*Corresponding author for this work

    Research output: Contribution to journalArticlepeer-review

    11 Citations (Scopus)
    Original languageEnglish
    Pages (from-to)293-296
    Number of pages4
    JournalInformation Processing Letters
    Volume89
    Issue number6
    DOIs
    Publication statusPublished (VoR) - 31 Mar 2004

    Keywords

    • Asynchronous logic
    • Formal methods
    • Formal verification
    • Specification languages

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