Optimization of drain current and voltage characteristics for DP4T double-gate RF CMOS switch at 45-nm technology

Viranjay M. Srivastava; K. S. Yadav; G. Singh

doi:10.1016/j.proeng.2012.06.060

Optimization of drain current and voltage characteristics for DP4T double-gate RF CMOS switch at 45-nm technology

Viranjay M. Srivastava^*, K. S. Yadav, G. Singh

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

3 Citations (SciVal)

Original language	English
Pages (from-to)	486-492
Number of pages	7
Journal	Procedia Engineering
Volume	38
DOIs	https://doi.org/10.1016/j.proeng.2012.06.060
Publication status	Published (VoR) - 2012
Event	International Conference on Modelling Optimization and Computing - TamilNadu, India Duration: 10 Apr 2012 → 11 Apr 2012

Keywords

45-nm technology
CMOS
Double-gate MOSFET
DP4T switch
Radio frcqucncy
RF switch
Single-gate MOSFET
VLSI

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10.1016/j.proeng.2012.06.060

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@article{a199e86f05dc4f1ba0b3bfb9c5365c84,

title = "Optimization of drain current and voltage characteristics for DP4T double-gate RF CMOS switch at 45-nm technology",

keywords = "45-nm technology, CMOS, Double-gate MOSFET, DP4T switch, Radio frcqucncy, RF switch, Single-gate MOSFET, VLSI",

author = "Srivastava, {Viranjay M.} and Yadav, {K. S.} and G. Singh",

year = "2012",

doi = "10.1016/j.proeng.2012.06.060",

language = "English",

volume = "38",

pages = "486--492",

journal = "Procedia Engineering",

issn = "1877-7058",

publisher = "Elsevier",

note = "International Conference on Modelling Optimization and Computing ; Conference date: 10-04-2012 Through 11-04-2012",

}

TY - JOUR

T1 - Optimization of drain current and voltage characteristics for DP4T double-gate RF CMOS switch at 45-nm technology

AU - Srivastava, Viranjay M.

AU - Yadav, K. S.

AU - Singh, G.

PY - 2012

Y1 - 2012

KW - 45-nm technology

KW - CMOS

KW - Double-gate MOSFET

KW - DP4T switch

KW - Radio frcqucncy

KW - RF switch

KW - Single-gate MOSFET

KW - VLSI

UR - http://www.scopus.com/inward/record.url?scp=84874882282&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84874882282&partnerID=8YFLogxK

U2 - 10.1016/j.proeng.2012.06.060

DO - 10.1016/j.proeng.2012.06.060

M3 - Conference article

AN - SCOPUS:84874882282

SN - 1877-7058

VL - 38

SP - 486

EP - 492

JO - Procedia Engineering

JF - Procedia Engineering

T2 - International Conference on Modelling Optimization and Computing

Y2 - 10 April 2012 through 11 April 2012

ER -

Optimization of drain current and voltage characteristics for DP4T double-gate RF CMOS switch at 45-nm technology

Keywords

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