Performance analysis of high-k dielectric based silicon nanowire gate-all-around tunneling FET

Shashi K. Dargar*, Viranjay M. Srivastava

*Corresponding author for this work

    Research output: Contribution to journalArticlepeer-review

    11 Citations (SciVal)
    Original languageEnglish
    Pages (from-to)340-345
    Number of pages6
    JournalInternational Journal of Electrical and Electronic Engineering and Telecommunications
    Volume8
    Issue number6
    DOIs
    Publication statusPublished (VoR) - 1 Nov 2019

    Keywords

    • Band-to-band tunneling
    • GAA structure
    • Nanotechnology
    • Si-nanowire
    • tunnel FET
    • VLSI

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