TY - GEN
T1 - Performance enhancement defect tolerance in the cell matrix architecture
AU - Saha, Chitta
AU - Bellis, S. J.
AU - Mathewson, A.
AU - Popovici, E. M.
PY - 2004/6/19
Y1 - 2004/6/19
N2 - This research concentrates on the area of fault tolerant circuit implementation in a field programmable type architecture, In particular, an architecture called the Cell Matrix, presented as a fault tolerant alternative to field programmable gate arrays using their Supercell approach, is studied. Architectural constraints to implement fault tolerant circuit design in this architecture are discussed. Some modifications of its basic Structure, such as the integration of circuitry for error correction and scan path, to enhance fault tolerant circuits design are introduced and are compared to the Supercell approach.
AB - This research concentrates on the area of fault tolerant circuit implementation in a field programmable type architecture, In particular, an architecture called the Cell Matrix, presented as a fault tolerant alternative to field programmable gate arrays using their Supercell approach, is studied. Architectural constraints to implement fault tolerant circuit design in this architecture are discussed. Some modifications of its basic Structure, such as the integration of circuitry for error correction and scan path, to enhance fault tolerant circuits design are introduced and are compared to the Supercell approach.
UR - https://pureportal.coventry.ac.uk/en/publications/performance-enhancement-defect-tolerance-in-the-cell-matrix-architecture(0b86c342-7b4e-460d-8458-faa3a4f85830).html
U2 - 10.1109/ICMEL.2004.1314949
DO - 10.1109/ICMEL.2004.1314949
M3 - Conference contribution
SN - 0-7803-8166-1
BT - 24th International Conference on Microelectronics, 2004
ER -