Reduction in parasitic capacitances for transmission gate with the help of CPL

Viranjay M. Srivastava, Rachit Patel, Harpreet Parashar, G. Singh

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    1 Citation (SciVal)
    Original languageEnglish
    Title of host publicationITC 2010 - 2010 International Conference on Recent Trends in Information, Telecommunication, and Computing
    Pages218-220
    Number of pages3
    DOIs
    Publication statusPublished (VoR) - 2010
    EventInternational Conference on Recent Trends in Information, Telecommunication, and Computing, ITC 2010 - Kochi, Kerala, India
    Duration: 12 Mar 201013 Mar 2010

    Publication series

    NameITC 2010 - 2010 International Conference on Recent Trends in Information, Telecommunication, and Computing

    Conference

    ConferenceInternational Conference on Recent Trends in Information, Telecommunication, and Computing, ITC 2010
    Country/TerritoryIndia
    CityKochi, Kerala
    Period12/03/1013/03/10

    Keywords

    • CPL
    • Delay time
    • Parasitic capacitance
    • Power dissipation
    • Speed performance of gate
    • Transmission gate
    • VLSI

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