@inproceedings{d554a06a7c9942e4934269065c08d7b5,
title = "Reduction in parasitic capacitances for transmission gate with the help of CPL",
keywords = "CPL, Delay time, Parasitic capacitance, Power dissipation, Speed performance of gate, Transmission gate, VLSI",
author = "Srivastava, {Viranjay M.} and Rachit Patel and Harpreet Parashar and G. Singh",
year = "2010",
doi = "10.1109/ITC.2010.67",
language = "English",
isbn = "9780769539751",
series = "ITC 2010 - 2010 International Conference on Recent Trends in Information, Telecommunication, and Computing",
pages = "218--220",
booktitle = "ITC 2010 - 2010 International Conference on Recent Trends in Information, Telecommunication, and Computing",
note = "International Conference on Recent Trends in Information, Telecommunication, and Computing, ITC 2010 ; Conference date: 12-03-2010 Through 13-03-2010",
}