Zero-Delay large signal convolution using multiple processor architectures

Nicholas Jillings; Joshua D. Reiss; Ryan Stables

doi:10.1109/WASPAA.2017.8170051

Zero-Delay large signal convolution using multiple processor architectures

Nicholas Jillings, Joshua D. Reiss, Ryan Stables

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

7 Citations (SciVal)

Original language	English
Title of host publication	2017 IEEE Workshop on Applications of Signal Processing to Audio and Acoustics, WASPAA 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	339-343
Number of pages	5
ISBN (Electronic)	9781538616321
DOIs	https://doi.org/10.1109/WASPAA.2017.8170051
Publication status	Published (VoR) - 7 Dec 2017
Event	2017 IEEE Workshop on Applications of Signal Processing to Audio and Acoustics, WASPAA 2017 - New Paltz, United States Duration: 15 Oct 2017 → 18 Oct 2017

Publication series

Name	IEEE Workshop on Applications of Signal Processing to Audio and Acoustics
Volume	2017-October

Conference

Conference	2017 IEEE Workshop on Applications of Signal Processing to Audio and Acoustics, WASPAA 2017
Country/Territory	United States
City	New Paltz
Period	15/10/17 → 18/10/17

Keywords

Convolution
Direct Form
GPU
Processor

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10.1109/WASPAA.2017.8170051

Cite this

Jillings, N., Reiss, J. D., & Stables, R. (2017). Zero-Delay large signal convolution using multiple processor architectures. In 2017 IEEE Workshop on Applications of Signal Processing to Audio and Acoustics, WASPAA 2017 (pp. 339-343). (IEEE Workshop on Applications of Signal Processing to Audio and Acoustics; Vol. 2017-October). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/WASPAA.2017.8170051

Jillings, Nicholas ; Reiss, Joshua D. ; Stables, Ryan. / Zero-Delay large signal convolution using multiple processor architectures. 2017 IEEE Workshop on Applications of Signal Processing to Audio and Acoustics, WASPAA 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 339-343 (IEEE Workshop on Applications of Signal Processing to Audio and Acoustics).

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title = "Zero-Delay large signal convolution using multiple processor architectures",

keywords = "Convolution, Direct Form, GPU, Processor",

author = "Nicholas Jillings and Reiss, {Joshua D.} and Ryan Stables",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 IEEE Workshop on Applications of Signal Processing to Audio and Acoustics, WASPAA 2017 ; Conference date: 15-10-2017 Through 18-10-2017",

year = "2017",

month = dec,

day = "7",

doi = "10.1109/WASPAA.2017.8170051",

language = "English",

series = "IEEE Workshop on Applications of Signal Processing to Audio and Acoustics",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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booktitle = "2017 IEEE Workshop on Applications of Signal Processing to Audio and Acoustics, WASPAA 2017",

}

Jillings, N, Reiss, JD & Stables, R 2017, Zero-Delay large signal convolution using multiple processor architectures. in 2017 IEEE Workshop on Applications of Signal Processing to Audio and Acoustics, WASPAA 2017. IEEE Workshop on Applications of Signal Processing to Audio and Acoustics, vol. 2017-October, Institute of Electrical and Electronics Engineers Inc., pp. 339-343, 2017 IEEE Workshop on Applications of Signal Processing to Audio and Acoustics, WASPAA 2017, New Paltz, United States, 15/10/17. https://doi.org/10.1109/WASPAA.2017.8170051

Zero-Delay large signal convolution using multiple processor architectures. / Jillings, Nicholas; Reiss, Joshua D.; Stables, Ryan.
2017 IEEE Workshop on Applications of Signal Processing to Audio and Acoustics, WASPAA 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 339-343 (IEEE Workshop on Applications of Signal Processing to Audio and Acoustics; Vol. 2017-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Reiss, Joshua D.

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KW - Direct Form

KW - GPU

KW - Processor

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M3 - Conference contribution

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SP - 339

EP - 343

BT - 2017 IEEE Workshop on Applications of Signal Processing to Audio and Acoustics, WASPAA 2017

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Y2 - 15 October 2017 through 18 October 2017

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Jillings N, Reiss JD, Stables R. Zero-Delay large signal convolution using multiple processor architectures. In 2017 IEEE Workshop on Applications of Signal Processing to Audio and Acoustics, WASPAA 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 339-343. (IEEE Workshop on Applications of Signal Processing to Audio and Acoustics). doi: 10.1109/WASPAA.2017.8170051

Zero-Delay large signal convolution using multiple processor architectures

Publication series

Conference

Keywords

Access to Document

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